The present invention relates to semiconductor memory devices and, more particularly, to a dynamic semiconductor memory device each cell of which consists of a transistor and a capacitor.
Dynamic random access memories (to be referred to as dRAMs hereinafter) are represented by a MOS dRAM having cells each consisting of a MOS capacitor and a MOS transistor (MOSFET). In dRAMs of this type, "1" or "0" digital data is stored in accordance with whether a charge is stored in its MOS capacitor or not. This data is read out by discharging the charge stored in the MOS capacitor of a selected cell to a corresponding pit line through a MOSFET and detecting a change in the potential of that bit line.
Increasing demands have arisen recently for a dRAM which has a large memory capacity. A dRAM can have a large memory capacity when packing density (i.e., density of memory cells) in chips of the same size is increased. The packing density of MOS dRAMs has been greatly improved due to new developments in recent semiconductor manufacturing techniques, particularly in micropatterning. As a result, it may be considered that a dRAM having a large memory capacity can be easily obtained by decreasing cell size on a chip substrate and increasing cell density.
However, when the cell size is just decreased, operational reliability of the dRAM is degraded. This is because the decrease in cell size also decreases its possible charging amount, which leads to degradation in the element characteristics. In other words, when the cell size is decreased, the size of a MOS capacitor in the cell is also decreased, resulting in a decrease in the capacitance of the MOS capacitor. Therefore, when the charging amount becomes less than a minimum level (required lower limit of the possible charging amount, determined by the operation margin of the cell and a margin against noise caused by incident .alpha. rays), basic cell characteristics are degraded. For this reason, miniaturization of the cell size, i.e., micropatterning of the dRAM, is limited.
The charging amount of the cell capacitor depends not only on the capacitance of the MOS capacitor but also on the value of the voltage applied thereto. It is theoretically possible to improve the charging amount of the cell capacitor by increasing the voltage applied thereto. In practice, however, increase in the applied voltage is not preferred since it requires increase in the power source voltage of the dRAM, which results in an increase in power consumption.
As methods for preventing decrease in the capacitance of the cell capacitor in manufacturing a dRAM with a large capacitance, the following three methods may be proposed:
(1) to decrease the thickness of the gate insulating film; PA1 (2) to increase dielectric constant of the gate insulating film; or PA1 (3) to increase the area of the capacitor electrode.
Among these, method (1) is limited in its application to a dRAM manufacturing process since the thickness of the gate insulating layer cannot be decreased drastically without degrading the reliability of the element characteristics. Therefore, method (1) cannot be adopted. In method (2), an insulating material having large dielectric constant would be used in place of silicon oxide (SiO.sub.2), which is currently under widespread use. However, no insulating material has yet been found which satisfies the above conditions and which can replace silicon oxide (a silicon compound such as Si.sub.3 N.sub.4 may be proposed as a substitute, but there are inherent problems in using such a compound in the mass production of highly reliable dRAMs.) Therefore, method (2) cannot be adopted, either. As a result, in order to increase the capacitance of the cell capacitor, method (3), i.e., a method to increase the area of the capacitor electrode, must be adopted.
In order to increase the area of the capacitor electrode without decreasing the packing density of the dRAM, cell capacitors are conventionally formed in grooves for separating cell regions on a substrate. More specifically, the cell capacitors are formed not on the cell regions defined by the grooves but in the grooves surrounding the island cell regions. In this case, the electrode of each cell capacitor also extends vertically along a recessed section of the groove. Therefore, the area of the capacitor electrode is substantially increased despite the small area of the grooves, resulting in great improvements in the effective capacitance of the cell capacitor.
However, in a conventional dRAM having the above arrangement, the area of the cell region is increased, and an expected improvement in higher packing density (larger memory capacity) of the dRAM cannot be obtained. This is because with the above arrangement, the cell transistor is constituted by a gate electrode provided on a periphery of the island cell region and a drain region formed at a central portion of the cell region. Therefore, the area of the MOS transistor in the cell is undesirably increased, and it is still difficult to enable a dRAM having good operational reliability and a large memory capacity (high packing density).